Data processing system are known in which, when in operation, a processing unit performs a certain task. The task may, for example, be the execution of a series of instructions defined by, for example, a computer program. Other devices or computer programs can have the processing unit perform requested services by generating interrupt requests. An interrupt request may for example be transmitted by a peripheral device to the processing unit. The interrupt request may for example be sent by an external memory device, such as a hard-disk, to signal the completion of task, such as a data transfer from or to the peripheral. Also, the interrupt request may for example be used to transmit information to the processing unit. For instance, a system timer may periodically transmit interrupt requests which can be used by the processing unit to establish a time-base.
The interrupt requests are propagated to an interrupt controller via multiple interrupt request lines. Once the interrupt controller identifies an active interrupt request line, it may grant the interrupt request and forward the interrupt request to the processing unit. In response to the interrupt request, the processing unit will interrupt the task being performed and perform a sequence of steps, generally referred to as an interrupt handler or interrupt service routine, associated with the requested interrupt.
However, a disadvantage of the use of interrupts is that the processing unit may be overloaded with the interrupt service routines.
European Patent EP 497 628 discloses a solution to avoid a central processing unit (CPU) in a multi processor circuit from being overloaded. This prior art document discloses a multi-processor circuit with a plurality of CPUs and an interrupt line for inputting interruption signals. The circuit further includes an interrupt restriction circuit connected between the interrupt line and each of the CPUs. The interrupt restriction circuit disables the input of the interruption signals to a CPU when the respective CPU has received a number of interruption signals in a specified time which exceeds a fixed number. However, a disadvantage thereof is that still a risk exists that the CPU is overloaded with requests, for instance in case a number of interrupt signals is received which is below the fixed number, but for each of which interrupt request the processing requires a large amount of CPU resources.
U.S. Pat. No. 6,889,277 discloses a system in which the period between successive interrupt requests is dynamically adjusted depending on a workload of a communication interface. However, a disadvantage thereof is that the CPU may be overloaded with requests.
United States Patent Application Publication US 2005/0177668 discloses a data processing system nested interrupt controller. The interrupt controller is responsive to priority level values associated with the respective interrupt handling programs to control the execution of the interrupt handlers. However, a disadvantage thereof is that overloading of the processing unit with interrupts is not prevented. For instance, the processing unit may receive a number of high priority interrupt requests which number exceeds the processing capacity of the processing unit.